1. Field of the Invention
This invention relates to semiconductor devices, and more particularly to diffused field effect transistors made from semiconductive materials and methods of forming the same.
2. Description of the Prior Art
Field effect transistors (FETs) have attained a great popularity and are in common use because of several distinct advantages over standard bipolar transistors. FETs are voltage controlled and have high input impedance. Also they are majority carrier devices, and exhibit neither thermal runaway nor minority carrier storage which reduces switching time. FET circuits are usually simpler than equivalent bipolar transistor circuits, requiring not only smaller but fewer components. Furthermore, an FET can be used as a resistor by making its channel region longer and narrower than in the transistor mode, and connecting its gate to a constant low voltage supply to keep it turned on. FETs used in this way as resistors are not much larger than normal FETs, whereas diffused resistors of the type used in bipolar integrated circuits, if they are to have appreciable resistance, must be quite long and occupy much more room than a bipolar transistor.
FETs are commonly formed in either a lateral configuration, with the gate, source and drain connections all made to one side of the chip, or in a vertical configuration with the gate and source connections on the upper side of the chip and the drain connection on the underside of the substrate. Such devices can suffer from the presence of parasitic bipolar transistors that are turned on by reverse current flows above a given threshold.
A standard vertical FET at an intermediate point in its manufacture is illustrated in FIG. 1. The device is formed on a semiconductive base member 2 which includes a lower n+ substrate 4, an n- drain layer 6 on top of the substrate, and a p body section 8 set in the drain layer. An n+ layer 10 is shown formed in part of the upper portion of body 8. Spaced layers of insulative material 12, 14, normally silicon dioxide, overlie the opposite ends of n+ layer 10 and the upper surface of body 8, and extend laterally over portions of the drain layer 6. Polysilicon members 16, 18 which have been rendered conductive by doping are deposited over respective insulative layers 12, 14.
In the final stage of manufacture, shown in FIG. 2, deposits of conductive material 20, 22 have been made over polysilicon members 16 and 18, respectively, to provide connections for the gates of two parallel FETs. Another metallic deposit 24 is made over the central portion of body 8, overlapping the ends of n+ sections 10a and 10b, to provide a common source connection for the parallel devices. A drain connection 26 is made at the underside of the substrate.
The finished device illustrated in FIG. 2 is referred to as a vertical diffused MOS (VDMOS) FET. In operation, channel regions 27, 28 are established in the body 8 immediately below each insulative layer 12, 14. N+ sections 10a and 10b serve in effect as extensions of the source, bringing the source for each device up to an edge of its channel region. The drain circuit is established through drain 26, substrate 4 and drain layer 6 to the opposite edge of each channel region. Signals applied to the two gate connections 20, 22 determine the extent and conductivity of their respective channel regions, and thereby control the source-drain currents for each device.
One of the principal problems associated with this type of FET is a substantially amount of resistance associated with the body region underlying each of the n+ source extensions 10a and 10b. In general, the amount of resistance presented to lateral current flows, from source 24 through each of the body extensions, varies in proportion to the length of sections 10a and 10b. Unfortunately, with presently available fabrication techniques it is not practical to extend the source connection 24 substantially closer to either of the gates so as to reduce the resistance under the n+ sections 10a, 10b. This limitation stems from the mask technique used to form the various elements of the device. Because of imperfect mask alignments, certain tolerances must be observed, resulting in a minimum spacing of about 6 microns between the source and drain. This lateral dimension results in an unnecessarily high resistance to lateral current flows, indicated by R in FIG. 2.
Under certain conditions, this resistance R can turn on parasitic transistors T1, T2 associated with the respective FETs. it can be seen that current flowing from n- drain layer 6 to source connection 24 must traverse the p body 8. Thus, each FET has an associated npn series of junctions which can be turned on under reverse breakdown or switching conditions to function as a parasitic bipolar transistor. If a lateral reverse current flow such as caused by an inductive load during turn-off through either body section R is large enough to develop a voltage greater than about 0.6 volts across the section, corresponding to the turn-on voltage threshold of a typical bipolar transistor, the corresponding parasitic bipolar transistor T1 or T2 will be turned on. This produces distortions in the operation and responsivity of the FET and may lead to failure.
In addition to the VDMOS devices discussed thus far, which are in common use for medium and high voltage applications, lateral diffused MOS (LDMOS) devices are used for lower voltage applications such as logic circuits. LDMOS FETs are also used for mixed technology devices using bipolar, CMOS and DMOS together. Lateral drain connections 30, 32 are indicated by dashed lines in FIG. 2. Each lateral drain connection would communicate with the edge of its respective channel region opposite to its respective source extension 10a or 10b by means of a lightly doped drift region or an n+ surface layer 34 or 36, which in effect extend the drains to the channel regions. With LDMOS devices the fabrication of the source and gates will be essentially the same as for the VDMOS devices, producing the same excess resistance problems associated with source extensions 10a and 10b; additional lateral resistances are associated with drain extensions 34 and 36. The substrate for lateral devices would normally be p type rather than n type as shown.
The prior art devices illustrated in FIGS. 1 and 2 have a particular polarity which yields npn parasitic transistors. A similar problem occurs if the polarities are reversed, but this time with pnp parasitic transistors.